The present invention relates to a method of manufacturing a semiconductor device exhibiting reduced capacitance loading. The present invention has particular applicability in manufacturing high density, multi-level semiconductor devices comprising sub-micron dimensions and exhibiting high circuit speed.
Interconnection technology is constantly challenged to satisfy the ever-increasing requirements for high density and performance associated with ultra large-scale integration semiconductor devices. The speed of semiconductor circuitry varies inversely with the resistance (R) and capacitance (C) of the interconnection system. The higher the value of the Rxc3x97C product, the more limiting the circuit speed. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Thus, the performance of multi-level interconnects is dominated by interconnect capacitance at deep sub-micron regimes. The rejection rate due to integrated circuits speed delays in sub-micron regimes has become a limiting factor in fabrication.
The dielectric constant of materials currently employed in the manufacture of semiconductor devices for an inter-layer dielectric (ILD) ranges from about 4.0 for dense silicon dioxide to over 8 for deposited silicon nitride. The value of the dielectric constant expressed herein is based upon a value of one for a vacuum. In an effort to reduce interconnect capacitance, dielectric materials with lower values of permittivity have been explored. The expression xe2x80x9clow-kxe2x80x9d material has evolved to characterize materials with a dielectric constant less than about 3.9.
ILD dielectric materials must be able to serve a number of different purposes requiring diverse characteristics and attributes. For example, the ILD material must: prevent unwanted shorting of neighboring conductors or conducting levels by acting as a rigid, insulating spacer; prevent corrosion and or oxidation of metal conductors, by acting as a barrier to moisture and mobile ions; fill deep, narrow gaps between closely spaced conductors; and undergo planarization of uneven surface topography so that a relatively flat level of conductors can be reliably deposited thereon. ILD films or layers must be formed at relatively low temperatures in order to avoid damage to or destruction of underlying conductors. In addition, many low-k dielectric materials have low oxide content which makes the material inadequate as an etch stop layer.
Silicon nitride has been the etch stop material of choice for making interconnect lines in low-k dielectric materials. However, silicon nitride has a relatively high dielectric constant (k of about 7) compared to the surrounding low-k dielectric layers. Furthermore, silicon nitride does not strongly adhere to organic doped silica glass (OSG) and fluorine doped silica glasses (FSG) low-k dielectrics.
One type of low-k material that has been explored are a group of flowable oxides which are basically ceramic polymers, such as hydrogen silsesquioxane (HSQ). Such polymers and their use are disclosed in, for example, U.S. Pat. No. 4,756,977 and U.S. Pat. No. 5,981,354. HSQ-type flowable oxides have been considered for gap filling between metal lines because of their flowability and ability to fill small openings. HSQ-type flowable oxides have been found to be vulnerable to degradation during various fabrication steps, including plasma etching. Methods involving plasma treatment have been developed to address such problems attendant upon employing HSQ-type flowable oxides as a gap filling layer, as in the U.S. Pat. No. 5,866,945 and U.S. Pat. No. 6,083,851.
There are several organic low-k materials, typically having a dielectric constant of about 2.0 to about 3.8, which offer promise for use as an ILD. Organic low-k materials which offer promise are carbon-containing dielectric materials such as FLARE 20198  dielectric, a poly(arylene) ether, available from Allied Signal, Advanced Micromechanic Materials, Sunnyvale, Calif.; BCB (divinylsiloxane bis-benzocyclobutene), and Silk(trademark), or porous Silk(trademark) dielectric, organic polymers similar to BCB, both available from Dow Chemical Co., Midland, Mich.; and organic doped silica glass (OSG) (also known as carbon doped glass) including Black-Diamond(trademark) dielectric available from Applied Materials, Santa Clara, Calif.; Coral(trademark) dielectric available from Novellus, San Jose, Calif., and Aurora(trademark) dielectric available from ASM America, Phoenix, Ariz.
In attempting to employ such carbon-containing low-k materials in interconnect technology, as for gap filling or as an ILD, it was found that their dielectric constant became undesirably elevated as a result of subsequent processing. For example, the dielectric constant of BCB was found to increase from about 2.6 to greater than about 4. It is believed that such an increase occurs as a result of exposure to an oxygen (O2) plasma stripping technique employed to remove photoresist material after formation of an opening in a dielectric layer, as, for example, a via hole or dual damascene opening for interconnecting metal features on different metal levels.
Other suitable types of low-k dielectrics are fluorine doped silica glasses (FSG). FSG include dielectrics formed from precursor gases SiF4, SiH4 and N2O and dielectrics formed from the precursors SiF4, tetraethylorthosilicate (TEOS), and O2. Dielectrics formed from TEOS and SiF4 are known as fluorinated TEOS or FTEOS. FSGs typically exhibit a dielectric constant of about 3.6. It is believed that fluorine lowers the dielectric constant of silicon oxide films because fluorine is an electronegative atom that decreases the polarizability of the overall SiOF network.
In addition to decreasing the dielectric constant, incorporating fluorine in silica layers can also improve the gap-filling properties of the deposited films. Because fluorine is an etching species, it is believed that fluorine etches the film as it is being deposited. The simultaneous deposition/etching effect preferentially etches the corners of a gap, keeping the gap open so that it fills with void-free FSG.
Unfortunately, there are several problems associated with some FSG layers. One problem is that a poorly formed FSG layer may absorb moisture from the atmosphere, or from the reaction products associated with the deposition. The absorption of water raises the dielectric constant of the FSG. Absorbed water may also interfere with subsequent wafer processing steps. For many applications, it is desirable that FSG layers do not desorb significant water vapor below about 450xc2x0 C.
Cap layers provide one method of reducing reabsorption of water into an FSG layer. The cap layer is typically undoped silica glass (USG) layer that is deposited onto an FSG layer with or without baking the FSG layer prior to depositing the cap. The cap may be formed in a separate deposition chamber or pump-down, or the process may be streamlined to follow the FSG layer deposition in the same chamber. Cap layers may provide acceptable protection from water absorption under many conditions.
Another problem associated with some FSG layers is corrosion. If fluorine is loosely bound into the FSG lattice, or has accumulated as free fluorine on the surface, the fluorine may combine with water to form hydrofluoric acid (HF). HF may corrode, and even destroy, other device features such as metal traces or anti reflective layers. One technique that is used to overcome the problems of corrosion is to form a liner over the substrate before depositing the FSG. The liner is typically a thin layer of USG that acts as a barrier between device features and the FSG.
A further problem with some FSG layers is that they are unstable. In other words, the layer characteristics change over time. For example, fully-formed FSG layers may form a cloudy haze, or even bubbles, within the layer when exposed to the atmosphere.
One problem with using a USG capping layer is that the USG capping layer does not adhere well to the fluorine-doped ILD surfaces. The poor adhesion of the capping layer to the ILD increases the likelihood of diffusion or leakage of conductive materials through the porous low-k ILD, which can lead to short circuits. In addition, both carbon and fluorine-doped low-k ILDs also exhibit inadequate adhesion to underlying semiconductor substrates.
The term semiconductor devices, as used herein, is not to be limited to the specifically disclosed embodiments. The semiconductor devices, as used herein, include a wide variety of electronic devices including flip chips, flip chip/package assemblies, transistors, capacitors, microprocessors, and random access memories, etc. In general, semiconductor devices refer to any electrical device comprising semiconductors.
There exists a need for efficient methodology enabling the use of low-k carbon and fluorine-doped dielectric materials as ILDs in high-density, multi-level connection patterns. There exists a particular need for methodology enabling the use of such low-k materials while avoiding their degradation from various fabrication steps subsequent to deposition. There further exists a particular need in this art to provide for strong adhesion of overlying layers to the ILD and for strong adhesion of the ILD to underlying semiconductor substrates.
These and other needs are met by embodiments of the present invention, which provide a method of forming a semiconductor device with a doped dielectric film on a semiconductor substrate. The dielectric film is formed by the steps of depositing a lower layer of a doped dielectric on a semiconductor substrate. The concentration of dopant is approximately constant throughout the lower layer. An upper layer of doped dielectric, wherein the concentration of dopant in the dielectric film is gradually reduced across the thickness of the upper layer, is deposited on the lower layer.
The earlier-stated needs are also met by another embodiment of the instant invention that provides a semiconductor device comprising a doped dielectric film formed on a semiconductor substrate. The doped dielectric film comprises a lower layer with an approximately constant dopant concentration throughout the lower layer. An upper layer, with a concentration of dopant that is gradually reduced from the concentration of the lower layer, is formed on the lower layer.
The foregoing and other features, aspects, and advantages of the present invention will become apparent in the following detailed description of the present invention when taken in conjunction with the accompanying drawings.